MetaMorph CPU
Hardware version of StageCore1. This processor is based on our DLX1-L FPGA micro module
and can be integrated into custom hardware. The underlying StageCore1 configuration and
firmware can be configured to run the application function.
With application functions usually being implemented on technologically less challenging
and more cost-efficient circuit board constructions, the integration of a performat processing
system usually scales disproportionate. Our CPU addresses this problem by offloading
complexity to a FPGA subprint with own memory and DC-DC converters.
Downloads
Management and Update Tool (NetView) - Java program located inside the zip file.
Firmware Bundle (StageCore1)
Module Pinout
Basic core and CPU signals
UART_LOG_TX | X1:35 | Console log (115 kBaud, 8Bit, 1Stop, no parity). StageCore1 uses this UART to send runtime log messages. |
UART_MON_RX | X1:39 | User monitor dialog (115 kBaud, 8Bit, 1Stop, no parity) |
UART_MON_TX | X1:37 | User monitor dialog (115 kBaud, 8Bit, 1Stop, no parity) |
RMII PHY (Micrel KSZ8021RNL or compatible)
RMII_CLK | X2:55 | RMII clock output |
RMII_RXD<0> | X2:47 | Receive data input [0] |
RMII_RXD<1> | X2:49 | Receive data input [1] |
RMII_RX_ER | X2:48 | Receive error input |
RMII_CRS_DV | X2:58 | Carrier sense / Receive data valid input |
RMII_TXD<0> | X2:54 | Transmit data output [0] |
RMII_TXD<1> | X2:56 | Transmit data output [1] |
RMII_TX_EN | X2:52 | Transmit enable output |
MII_MDC | X2:51 | Management interface (MII) clock output |
MII_MDIO | X2:53 | Management interface (MII) data I/O |
ETH_PHY_RST_N | X2:60 | PHY reset output, active low, needs external 4k7 pulldown |
ETH_PHY_IRQ_N | X2:50 | PHY interrupt input, active low |
ETH_PEER_LED | X2:59 | Peer LED (low = on, Z = off) |
System status
READY | X1:41 | System ready condition (everything up and running). Can be used in a condition to open an interlock. |
ERROR_LED | X2:45 | Error LED (red, low = on, Z = off) |
SESSION_LED | X2:41 | Session LED (blue, low = on, Z = off), this LED is controlled by the IDN server and signals an active session. |
BRIDGE_LED | X2:43 | Bridge LED (blue, low = on, Z = off), this LED is controlled by the feed client and signals an active bridge. |
MATE_STATUS1_LED | X2:33 | Mate status LED (green, low = on, Z = off) |
MATE_STATUS2_LED | X2:35 | Mate status LED (green, low = on, Z = off) |
FEED_STATUS1_LED | X2:37 | Feed status LED (green, low = on, Z = off) |
FEED_STATUS2_LED | X2:39 | Feed status LED (green, low = on, Z = off) |
PUSH_BUTTON | X1:52 | Push button used for communication/firmware reset and pairing |
I²C
A 24C64 type EEPROM (or compatible) shall be reachable at address 0xA8
IIC_SCL | X1:38 | Needs external pullup |
IIC_SDA | X1:40 | Needs external pullup |
Laser projector: Common converter signals
CV_CLK1 | X1:12 | DAC clock output (galvo, laser, color) |
CV_CLK2 | X1:29 | 16 Bit ADC clock output |
CV_CLK3 | X1:30 | 12 Bit ADC clock output |
Laser projector: Galvo commands and feedback
Converters used: AD5662xRJ-2 or compatible
G1C_CS | X1:17 | Port 1 galvo chip select output |
G1CX_D | X1:19 | Port 1 galvo X output (ISP out: X) |
G1CY_D | X1:21 | Port 1 galvo Y output (ISP out: Y) |
G2C_CS | X2:18 | Port 2 galvo chip select output |
G2CX_D | X2:20 | Port 2 galvo X output (ISP out: U4) |
G2CY_D | X2:22 | Port 2 galvo Y output |
Laser projector: Laser commands and feedback
The timing of these signals is referenced to the galvo signals (Blankshift). Converters used: DAC7311IDCK or compatible
L1_CLR | X1:2 | Port 1 laser clear output (ISP out: Shutter). This signal indicates the intention of laser emission (low = dark, high = emission). |
L1C_CS | X1:4 | Port 1 chip select output |
L1C_D | X1:6 | Port 1 data output (ISP out: Intensity) |
L2_CLR | X2:1 | Port 2 laser clear output. This signal indicates the intention of laser emission (low = dark, high = emission). |
L2C_CS | X2:3 | Port 2 chip select output |
L2C_D | X2:5 | Port 2 data output |
Laser projector: Color line commands
The timing of these signals is referenced to the laser control signals and can be individually tweaked. Converters used: DAC7311IDCK or compatible
A1_CS | X1:14 | Port 1 line A chip select output |
A1_D | X1:16 | Port 1 line A data output (ISP out: R) |
B1_CS | X1:18 | Port 1 line B chip select output |
B1_D | X1:20 | Port 1 line B data output (ISP out: G) |
C1_CS | X1:22 | Port 1 line C chip select output |
C1_D | X1:24 | Port 1 line C data output (ISP out: B) |
D1_CS | X1:26 | Port 1 line D chip select output |
D1_D | X1:28 | Port 1 line D data output |
A2_CS | X2:13 | Port 2 line A chip select output |
A2_D | X2:15 | Port 2 line A data output (ISP out: U1) |
B2_CS | X2:17 | Port 2 line B chip select output |
B2_D | X2:19 | Port 2 line B data output (ISP out: U2) |
C2_CS | X2:21 | Port 2 line C chip select output |
C2_D | X2:23 | Port 2 line C data output (ISP out: U3) |
D2_CS | X2:25 | Port 2 line D chip select output |
D2_D | X2:27 | Port 2 line D data output |
Laser projector: Other signals
ISP_DMX_OUT | X1:36 | DMX512 output according to ISP-DMX standard |
Laser projector: ILDA Standard Projector (ISP) input
Converters used: ADS8326(16 Bit) and ADS7866(12 Bit) or compatible
ISP_CS16 | X2:9 | 16 bit converter chip select output |
ISP_CS12 | X2:5 | 12 bit converter chip select output |
ISP_X | X2:7 | X converter data input (16 Bit) |
ISP_Y | X2:3 | Y converter data input (16 Bit) |
ISP_I | X2:29 | I converter data input (12 Bit) |
ISP_R | X2:30 | R converter data input (12 Bit) |
ISP_G | X2:31 | G converter data input (12 Bit) |
ISP_B | X2:32 | B converter data input (12 Bit) |
ISP_U1 | X1:32 | U1 converter data input (12 Bit) |
ISP_U2 | X1:31 | U2 converter data input (12 Bit) |
ISP_U3 | X1:34 | U3 converter data input (12 Bit) |
ISP_U4 | X1:33 | U4 converter data input (16 Bit) |
ISP_CLR | X2:1 | Shutter input |
ISP_ITX | X2:10 | Interlock transmit output |
ISP_IRX | X2:12 | Interlock receive output |
ISP_DMX_IN | X1:44 | DMX512 input according to ISP-DMX standard |
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